1. Field of the Invention
The present invention relates to semiconductor packaging.
2. Description of the Related Art
A popular, thin chip size package (CSP) for housing a semiconductor die includes a thin substrate with an insulative core layer overlaid by metal circuit patterns and an outermost protective layer. The core layer has a central through hole, i.e., an aperture entirely through the substrate. The semiconductor die is electrically coupled to the circuit patterns by bond wires. The semiconductor die is disposed in the through hole, and is supported in the through hole by a hardened encapsulant. The encapsulant fills the through hole around the semiconductor die, and covers the active surface and peripheral sides of the semiconductor die, the bond wires, and a portion of a first side of the substrate around the through hole. An inactive surface of the semiconductor die is exposed in a common plane with a second side of the substrate and a planar portion of the encapsulant. After the encapsulation process, a plurality of same-size (within a manufacturing tolerance) solder balls are fused to the circuit patterns of one of the sides of the substrate. The user of the package electrically couples the package to an external printed circuit board by positioning the package so that the solder balls are each juxtaposed with a metal trace of the printed circuit board, and then reflowing the solder balls so that the solder balls are fused to the metal traces of the printed circuit board.
During the encapsulation process, a heated resin encapsulant, such as epoxy molding compound (EMC), is injected into the through hole and onto the semiconductor die. The resin encapsulant hardens while cooling to room temperature. However, because the semiconductor die, the EMC, and the substrate have different thermal properties, e.g., experience different amounts of expansion or contraction with temperature, and because the substrate is so thin, the encapsulated semiconductor package is prone to warpage due to the relative over-contraction of the EMC. This post-encapsulation warpage phenomenon increases exponentially as the area of the substrate increases, which acts as a limit on the size of the semiconductor die that can be housed in the package. Further, when the warpage is present, the solder balls do not all have their bottom surfaces at the same level, i.e., in a common plane, as is intended. Solder balls in an outermost row of solder balls near a perimeter of the substrate are most likely to be affected, e.g., to have their bottom surfaces in a plane above the plane formed by the bottom surfaces of the remainder of the solder balls. Accordingly, the affected solder balls do not fuse to, or form a poor quality fuse with, the juxtaposed metal traces of the external printed circuit board during the reflowing process, resulting in an electric connection failure or an increased likelihood of an electric connection failure. Obviously, semiconductor package manufacturers must help the package user to avoid such problems.